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Traffic VHDL simulation issues

I have updated the program, it does finish but now I am trying simulate the project. I am able to get the clock clear and lights on the pins, but I am not able to get the lights to work and count and states are not even showing. I believe I have this all set correctly but I could be wrong. Thank you once again Morten Zilmer for the help with the Error code.

http://tinypic.com/r/24yog0z/8

This is the simulation of the file, simulation image

entity traffic is
port    (clk: in std_logic;
         clr: in std_logic;
         lights: out std_logic_vector (5 downto 0));
 end traffic;

 architecture traffic of traffic is
 type state_type is (s0, s1, s2, s3, s4, s5);
 signal state: state_type;
 signal count : std_logic_vector (3 downto 0);
 constant sec5: std_logic_vector (3 downto 0) := "1111";
 constant sec1: std_logic_vector (3 downto 0) := "0011";

 begin
 process(clk, clr)
 begin
if clr = '1' then
        state<= s0;
        count <= x"0";
elsif (clk'event and clk = '1') then
    case state is
    when s0 =>
        if count <= sec5 then
            state <= s0;
            count <= count +1;
        else
            state <= s1;
            count <= x"0";
            end if;
    when s1 =>
        if count <= sec1 then
            state <= s1;
            count <= count +1;
        else
            state <= s2;
            count <= x"0";
            end if;
    when s2 =>
        if count <= sec1 then
            state <= s2;
            count <= count +1;
        else
            state <= s3;
            count <= x"0";
            end if;
    when s3 =>
        if count <= sec5 then
            state <= s3;
            count <= count +1;
        else
            state <= s4;
            count <= x"0";
            end if;
    when s4 =>
        if count <= sec1 then
            state <= s4;
            count <= count +1;
        else
            state <= s5;
            count <= x"0";
            end if;
    when s5 =>
        if count <= sec1 then
            state <= s5;
            count <= count +1;
        else
            state <= s0;
            count <= x"0";
            end if;
    when others =>
            state <= s0;
end case;
end if;
end process;

c2 : process (state)
begin
case state is
    when s0 => lights <= "100001";
    when s1 => lights <= "100010";
    when s2 => lights <= "100100";
    when s3 => lights <= "001100";
    when s4 => lights <= "010100";
    when s5 => lights <= "100100";
    when others => lights <= "100001";
    end case;
end process;
end traffic;
Solution

  • Change elseif to elsif, for valid VHDL syntax.