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vhdl

Implements a 4 input xor using a 2 input xor code

Let's say that i only have the entity below of a 2 input XOR to create a a 4 input XOR.

entity exclusive_or is
 port(A,B: in BIT; S: out BIT);
end exclusive_or;

I know i have to declare some signals, but don't know how.

Solution

  • First, let's draw on paper what we want to do:

    schematic

    Then, we convert this to VHDL:

    entity exclusive_or_4 is port(
    A,B,C,D: in BIT;
    S: out BIT
);
end entity;

architecture rtl of exclusive_or_4 is
    signal output : bit_vector(1 downto 0);
begin

    U0: component exclusive_or port map (
        A => A,
        B => B,
        S => output(0)
    );

    U1: component exclusive_or port map (
        A => C,
        B => D,
        S => output(1)
    );

    U2: component exclusive_or port map(
        A => output(0),
        B => output(1),
        S => S
    );

end architecture;