VHDL Configuration cannot find component

Question

The code below is not working correctly. I keep getting the following errors:

** Error: HA_Config.vhd(38): Component instance "HA_Inst : HA_Comp" not found. ** Error: HA_Config.vhd(40): VHDL Compiler exiting

library ieee;
use ieee.std_logic_1164.all;

entity HA_Entity is
  port (
    i_bit1  : in std_logic;
    i_bit2  : in std_logic;
    --
    o_sum   : out std_logic;
    o_carry : out std_logic
    );
end HA_Entity;


architecture HA_Arch of HA_Entity is

  component HA_Comp is
    port (
      i_bit1  : in  std_logic;
      i_bit2  : in  std_logic;
      --
      o_sum   : out std_logic;
      o_carry : out std_logic
      );
  end component HA_Comp;

begin 

  o_sum   <= i_bit1 xor i_bit2;
  o_carry <= i_bit1 and i_bit2;

end HA_Arch;

configuration HA_Config of HA_Entity is
  for HA_Arch  
    for HA_Inst : HA_Comp
      use entity HA_Entity(HA_Arch);
    end for;
  end for;
end HA_Config;

Answer 1

A configuration binds a component instance to a specific entity and architecture. The binding part in the configuration is:

for HA_Inst : HA_Comp
  use entity HA_Entity(HA_Arch);
end for;

But there is no component instance named HA_Inst of the component HA_Comp, just a declared component HA_Comp in the architecture part of HA_Arch, thus the error:

Component instance "HA_Inst : HA_Comp" not found.

The HA_Comp is actually not used anywhere, so it could be removed. Also, it looks like a circular reference since HA_Entity is specified for use inside itself with configuration ... HA_Entity ... use entity HA_Entity ....

If the intention is to allow different implementations of HA_Arch, then it can look like:

library ieee;
use ieee.std_logic_1164.all;

entity HA_Entity is
  port (
    i_bit1  : in std_logic;
    i_bit2  : in std_logic;
    --
    o_sum   : out std_logic;
    o_carry : out std_logic
    );
end HA_Entity;


architecture HA_Arch of HA_Entity is

  component HA_Comp is
    port (
      i_bit1  : in  std_logic;
      i_bit2  : in  std_logic;
      --
      o_sum   : out std_logic;
      o_carry : out std_logic
      );
  end component HA_Comp;

begin

  HA_Inst : component HA_Comp
    port map(
      i_bit1 => i_bit1,
      i_bit2 => i_bit2,
      o_sum  => o_sum,
      o_carry => o_carry);

end HA_Arch;


library ieee;
use ieee.std_logic_1164.all;

entity HA_Comp_Entity is
  port (
    i_bit1  : in std_logic;
    i_bit2  : in std_logic;
    --
    o_sum   : out std_logic;
    o_carry : out std_logic
    );
end HA_Comp_Entity;

architecture HA_Comp_Arch_1 of HA_Comp_Entity is
begin

  o_sum   <= i_bit1 xor i_bit2;
  o_carry <= i_bit1 and i_bit2;

end HA_Comp_Arch_1;


use work.all;

configuration HA_Config of HA_Entity is
  for HA_Arch
    for HA_Inst : HA_Comp
      use entity HA_Comp_Entity(HA_Comp_Arch_1);
    end for;
  end for;
end HA_Config;