Here is an example of out of order pipeline from "The Intel Microprocessor Family" by James Antonakos.
Consider this sequence of instructions. The number of clock cycles assigned to each instruction is fabricated for this example.
1: MOV AL, 2 ; 1 cycle
2: MOV DL, [SI] ; 3 cycles
3: MUL DL ; 2 cycles
4: INC SI ; 1 cycle
5: SUB BX, 4 ; 1 cycle
6: ADD AX, BX ; 1 cycle
7: MOV CX, 2000 ; 1 cycle
Scheduling instructions in order between two pipelines: (I know the basic concept of this.)
Clock Cycle Pipeline # 1 Pipeline # 2
1 MOV AL, 5 MOV DL, [SI]
2 idle busy
3 idle busy
4 MUL DL INC SI
5 busy SUB BX, 4
6 ADD AX, BX MOV CX, 2000
Scheduling instructions out of order between two pipelines:
Clock Cycle Pipeline # 1 Pipeline # 2
1 MOV AL, 5 MOV DL, [SI]
2 INC SI SUB BX, 4
3 MOV CX, 2000 busy
4 MUL DL idle
5 ADD AX, BX idle
Can someone explain to me how out of order pipeline is done? Thank you!
The out of order engine will simply take any ready (ones that aren't waiting on any dependencies) opcodes (instructions that have been broken down into multiple parts) and schedule them for execution. How far it looks ahead depends on how many instructions have been fetched and decoded by the front end.
In your out of order example, you won't be able to execute the "INC SI" until after the "MOV DL, [SI]" has ready SI and gone through AGEN (address generation) to load from. The "SUB BX, 4", however, has no dependencies and is ready to get scheduled to execute whenever the HW sees it, etc..