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loopsvhdlfpga

What is the iteration error in the loop?


loop
                if rising_edge (CLOCK) then   
                fcounter := fcounter+1;         
                end if;

                A<=fcounter(6);           --fa=fclock/2^6

                if rising_edge (A) then  
                counter_A:= counter_A+1;              
                end if;

                CIKIS<=A; --40 consecutive "1" consignment to DIN for STARTUP RESET 
                exit when counter_A=101000; --40
end loop;

ISE gives "ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." What does that mean and what should i do to get rid of it?


Solution

  • Unbounded loops are not generally synthesizable outside of generating constants. The error is telling you that the loop has iterated beyond the preset limit that guards against infinite loops. Increasing the limit will not fix anything because what you have described doesn't map naturally to hardware with the current crop of synthesis tools.

    You need to restructure your logic to inhibit that block of code with an enable that is deactivated when the counter reaches its terminal value rather than use a loop.