What does "others=>'0'" mean in an assignment statement?

Question

cmd_register: process (rst_n, clk)
begin
   if (rst_n='0') then
    cmd_r<= (others=>'0');
   elsif (clk'event and clk='1') then
    cmd_r<=...;
   end if;
end process cmd_register;

I know "<=" specifies assignment but what is others? And what does => do?

Answer 1

cmd_r is defined as a std_logic_vector, or unsigned or signed signal. let's see how this signal type are defined:

type std_logic_vector is array (natural range <>) of std_logic; 
type unsigned         is array (natural range <>) of std_logic; 
type signed           is array (natural range <>) of std_logic;

Note that these 3 types have the same definition as an array of std_logic items.

The statement "Others => '0'" is a feature of the VHDL when the coder want to defined several items in an array with the same value.

In your example, all item std_logic in the array are set to '0'.

Another application of this statement is to set some items at a specific value and all others at a default value :

cmd_r <= (0      => '1',
          4      => '1',
          others => '0');

In this case, the bit 0 and 4 are set to '1' and all other bits are set to '0'.

One last thing, it's NOT possible to write something like this :

  cmd_r <= (0          => '1',
            4 downto 2 => "111", -- this line is wrong !!!
            others     => '0');