Can anyone who is an expert in HDL (VHDL/Verilog) give insight on the following:
I know that for simple designs, either would be sufficient.
However, in what cases is one approach better the other? I've gotten opinion that for complex designs, a schematic editing workflow ends up being harder to maintain. Is this true in practice?
I've only experience in Xilinx ISE but im well aware of other tools out there
All the lower-level HDL modules I code by hand because in most cases you need fine control over how everything behaves. A tool may allow you to drag and drop in what you need, but you're limited to what they have in the toolset. Coding by hand allows you to do anything you want to and also allows you to minimise resource usage and only use BRAMS/resources where necessary. I have found that the HDL generated by a schematic editor tends to use more of the FPGA resources than one coded by hand.
Another point is that often HDL builds are scripted and the GUI tools are not used for final builds. Since the schematic editor is gui based, it's more difficult to automate a schematic build.
Having said all that, schematic editing is great for putting together the top level of a design, that is, wiring all the existing HDL blocks together. Rather than describing the behaviour of the low-level stuff, this is just a nice way of visualising how everything fits. I have recently been coding my own custom HDL IP by hand and using those in the Vivado schematic editor. It has worked quite well, so it really depends on how the tools are being used.