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VHDL Simulation Timing Behaviour

I'm trying to write some VHDL code that simply feeds sequential bits from a std_logic_vector into a model of an FSM. However, the bits don't seem to be updating correctly. To try figure out the issue, I have the following code, where instead of getting a bit out of a vector, I'm just toggling the signal x (the same place I'd be getting a bit out).

    clk <= NOT clk after 10 ns;
    process(clk) 
        begin
            if count = 8 then
                assert false report "Simulation ended" severity failure;
            elsif (clk = '1') then
                x <= test1(count);
                count <= count + 1;
            end if;         
    end process;

EDIT: It appears I was confused.I've put it back to trying to take bit by bit out of the vector. This is the output. I would have thought that on when count is 1, x would take on the value of test1(1) which is a 1.

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Solution

  • As David points out in the comments, the code is working fine. The issue was my ignorance of bit order in the std_logic_vector.