Accessing SystemVerilog code during simulation

Question

I'm exploring SystemVerilog right now and looking for possibilities to change the testbench state during simulation. The obvious way is forcing signals, variables, whatsoever. Are there other ways? Really nice would be a possibility to stop the simulation and call SystemVerilog functions (or class methods) from the ModelSim console. Do you know a way to do it?

Answer 1

Starting with ModelSim 10.2, you can use the call Tcl command to call a SystemVerilog function or method from the command line.

This is intended for debugging only. For performance reasons, you should always write your testbench in SystemVerilog, not Tcl.