include source files using path in makefile

Question

I have one directory called MAKE and two sub directory's source and header. source contains cpp files and header contains one header file which is included in all three cpp files. I am trying to create a make file. i am trying to access the source and header files from the directories. my current directory is MAKE(where my make file is present).

I am getting error as NO rule to target. Stop Where am i going wrong

    CC = g++
    INC_SOURCE = -I/home/abhiskekkumar/Desktop/VINEETH/Make/source/
    INC_DEST =  -I/home/abhiskekkumar/Desktop/VINEETH/Make/header
    SOURCE = $(shell echo *.cpp)
    HEADER = $(shell echo *.h)
    OBJECT = $(SOURCE:.cpp=.o)
    TARGET = output

    EXEC: $(TARGET)
            ./output
    $(TARGET): $(OBJECT)
            $(CC) $(INC_SOURCE) $(INC_DEST) -o $(TARGET) $(OBJECT)

Answer 1

 CC = g++
 TARGET = vineeth

 CFLAGS   = -Wall

 LINKER   = g++ -o


SRCDIR   = source
HEADDIR  = header
OBJDIR   = obj
BINDIR   = bin

SOURCES  := $(wildcard $(SRCDIR)/*.cpp)
INCLUDES := $(wildcard $(HEADDIR)/*.h)
OBJECTS  := $(SOURCES:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)


$(BINDIR)/$(TARGET): $(OBJECTS)
     $(LINKER) $@ $(LFLAGS) $(OBJECTS)
     @echo "Linking complete!"

$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
     @$(CC) $(CFLAGS) -c $< -o $@
     @echo "Compiled "$<" successfully!"