As an aid to understanding the x86 instruction set, I've been trying out various forms of mov in NASM and comparing the generated code with the opcodes listed in the Intel documentation. Most of them come out as I expected, but there's one I can't seem to get NASM to generate:
a1 mov eax,moffs32
In particular, this doesn't do it (assembles to a different opcode instead):
mov eax,[44332211h]
Same goes for the 64-bit variant and the inverse opcode a3. How do you get the assembler to generate these opcodes? Am I misunderstanding what 'memory offset' means?
NASM is probably picking a shorter variant. In 64-bit addressing mode the A1 opcode has a 64-bit address making the instruction 9 bytes long: A1 11 22 33 44 00 00 00 00. By picking an opcode with an ModR/M encoding it lets use a 32-bit offset instead resulting a 7 byte long instruction. Eg: 8B 04 25 11 22 33 44