i'm trying to implement floating point multiplier module using xilinx ip cores for matrix multiplication and i get warnings for all the components output saying like that NgdBuild:443 - SFF primitive 'Multiplication.M44/blk00000003/blk0000057e' has unconnected output pin here is the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Multiplier is
GENERIC( N : integer := 4);
PORT(
clock,reset : IN STD_LOGIC;
Aport: IN STD_LOGIC_VECTOR(31 downto 0);
Bport: IN STD_LOGIC_VECTOR(31 downto 0);
Xport:out STD_LOGIC_VECTOR(31 downto 0)
);
end Multiplier;
architecture Behavioral of Multiplier is
type N_array is array (0 to N- 1) of STD_LOGIC_VECTOR (31 downto 0);
type NfN is array (0 to N - 1) of N_array;
TYPE state IS (state0, state1);
SIGNAL pr_state, nx_state: state;
SIGNAL Ain_reg,Ain_next :NfN;
SIGNAL Bin_reg,Bin_next :N_array;
signal mul1,mul2,mul3,mul4,sum1,sum2 :N_array ;
signal prod_reg,prod_next:N_array;
Signal s_reg, s_next: INTEGER RANGE 0 TO 20;----used as counter
Signal P_reg, P_next: INTEGER RANGE 0 TO 10;----used as counter
Signal Address_reg, Address_next: INTEGER RANGE 0 TO 10;----used as counter
Signal out_reg,out_next: STD_LOGIC_VECTOR(31 downto 0);
---------------------------------------------------------------------------------------
--Declaration of type and signal of a N element RAM
--and a type and signal of a NXN element RAM
--with each element being 32 bit wide.
type ram_t is array (0 to N) of std_logic_vector(31 downto 0);
type ram_array is array (0 to N*n) of std_logic_vector(31 downto 0);
signal ram_B : ram_t := (others => (others => '0'));
signal ram_out : ram_t := (others => (others => '0'));
signal ram_A : ram_array := (others => (others => '0'));
--------------------------------------------------------------------------------------
----------Components------------------------------------------------------------------
--This is the floating point 5 components adjusted to be used with virtex6
component Adder
port (
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
clk: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0));
end component;
------------------------------------------------------
component Multi
port (
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
clk: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0));
end component;
--------------------------------------------------------------------------------------
BEGIN
--------------------------------------------------------------------------------------
Multiplication:BLOCK
Begin
M11:Multi port map (a => Ain_reg(0)(0),b => Bin_reg(0),clk => clock,result => mul1(0));
M12:Multi port map (a => Ain_reg(0)(1),b => Bin_reg(1),clk => clock,result => mul2(0));
M13:Multi port map (a => Ain_reg(0)(2),b => Bin_reg(2),clk => clock,result => mul3(0));
M14:Multi port map (a => Ain_reg(0)(3),b => Bin_reg(3),clk => clock,result => mul4(0));
S11: Adder port map (a =>mul1(0),b => mul2(0),clk => clock,result => sum1(0));
S12: Adder port map (a =>mul3(0),b => mul4(0),clk => clock,result => sum2(0));
PROD1: Adder port map (a => sum1(0),b =>sum2(0),clk => clock,result => prod_next(0));
M21:Multi port map (a => Ain_reg(1)(0),b => Bin_reg(0),clk => clock,result => mul1(1));
M22:Multi port map (a => Ain_reg(1)(1),b => Bin_reg(1),clk => clock,result => mul2(1));
M23:Multi port map (a => Ain_reg(1)(2),b => Bin_reg(2),clk => clock,result => mul3(1));
M24:Multi port map (a => Ain_reg(1)(3),b => Bin_reg(3),clk => clock,result => mul4(1));
S21:Adder port map (a => mul1(1),b => mul2(1),clk => clock,result => sum1(1));
S22:Adder port map (a => mul3(1),b => mul4(1),clk => clock,result => sum2(1));
PROD2:Adder port map (a => sum1(1),b =>sum2(1),clk => clock,result => prod_next(1));
M31:Multi port map (a => Ain_reg(2)(0),b => Bin_reg(0),clk => clock,result => mul1(2));
M32:Multi port map (a => Ain_reg(2)(1),b => Bin_reg(1),clk => clock,result => mul2(2));
M33:Multi port map (a => Ain_reg(2)(2),b => Bin_reg(2),clk => clock,result => mul3(2));
M34:Multi port map (a => Ain_reg(2)(3),b => Bin_reg(3),clk => clock,result => mul4(2));
S31:Adder port map (a => mul1(2),b => mul2(2),clk => clock,result =>sum1(2));
S32:Adder port map (a => mul3(2),b => mul4(2),clk => clock,result =>sum2(2));
PROD3:Adder port map (a => sum1(2),b =>sum2(2),clk => clock,result => prod_next(2));
M41:Multi port map (a => Ain_reg(3)(0),b => Bin_reg(0),clk => clock,result => mul1(3));
M42:Multi port map (a => Ain_reg(3)(1),b => Bin_reg(1),clk => clock,result => mul2(3));
M43:Multi port map (a => Ain_reg(3)(2),b => Bin_reg(2),clk => clock,result => mul3(3));
M44:Multi port map (a => Ain_reg(3)(3),b => Bin_reg(3),clk => clock,result => mul4(3));
S41: Adder port map (a => mul1(3),b => mul2(3),clk => clock,result => sum1(3));
S42: Adder port map (a => mul3(3),b => mul4(3),clk => clock,result => sum2(3));
PROD4:Adder port map(a => sum1(3),b => sum2(3),clk => clock,result => prod_next(3));
end BLOCK Multiplication;
---------- Lower section: ------------------------
PROCESS (reset, clock)
BEGIN
IF (reset='1') THEN
pr_state <= state0;
address_reg <= 0;
s_reg <= 0;
P_reg <= 0;
ELSIF (clock'EVENT AND clock='1') THEN
pr_state <= nx_state;
s_reg <= s_next;
p_reg <= p_next;
Address_reg <= Address_next;
Ain_reg <= Ain_next;
Bin_reg <= Bin_next;
prod_reg<=prod_next;
out_reg<=out_next;
END IF;
END PROCESS;
---------- Upper section: ------------------------
PROCESS (Bport,Aport,out_reg,Address_reg,pr_state,s_reg,Ain_reg,Bin_reg,prod_reg,p_reg)
BEGIN
Address_next <= Address_reg ;
s_next <= s_reg;
p_next <= p_reg;
Bin_next <= Bin_reg ;
Ain_next <= Ain_reg;
out_next <= out_reg;
nx_state <= pr_state ;
CASE pr_state IS
WHEN state0 =>
IF (s_reg < N) THEN
Bin_next(s_reg) <= Bport;
Ain_next(0)(s_reg) <= Aport;
s_next <= s_reg + 1;
ELSif(s_reg > 3 and s_reg < 8) then
Ain_next(1)(4-s_reg) <= Aport;
s_next <= s_reg + 1;
ELSif(s_reg > 7 and s_reg < 12) then
Ain_next(2)(8-s_reg) <= Aport;
s_next <= s_reg + 1;
ELSif(s_reg > 11 and s_reg < 16) then
Ain_next(3)(12-s_reg) <= Aport;
s_next <= s_reg + 1;
ElSE
s_next <= 0;
nx_state <= state1;
END IF;
WHEN state1 =>
IF (P_reg < N) THEN
out_next<= prod_reg(P_reg);
P_next <= P_reg + 1;
ELSE
--- P_next <= 0;
nx_state <= state0;
END IF;
END CASE;
END PROCESS;
Xport <= out_reg ;
end Behavioral;
Probably you didn't enable some of the optional features of the IP core. The netlist however, does contain ports for these features. According to AR21718 you can safely ignore this type of warnings as the unused elements will be trimmed out during MAP phase.