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vhdldigitalregister-transfer-levelvlsi

multiple assignment of concurrent statement


The following code gives me an error, which I can't figure out myself. The error is because there are multiple assignments of output d0

do: for i in 0 to 9 generate
  d0<=di0(129-i downto 120-i)
       when f(i)='1';
end generate do;

Solution

  • A for-generate creates concurrent logic that is replicated multiple times. You have specified 10 assignments to d0. Effective use of generate statements typically requires the use of array types as the targets of assignments to organize the different concurrent elements. Optionally, you may be able to use resolved types to manage multiple drivers of a single signal but that isn't typically useful outside of simulation.

    It looks like you're trying to describe a mux using a one-hot selection. This can be accomplished without a generate statement. Think about the logic involved in creating a mux and describe the relevant boolean operations in parallel using arrays.