Variable and constants in VHDL

Where the KEYWORDS variable and constant have to be used in VHDL coding, I'm aware of the scope of both of them, but unable to figure out which one has to be used when??

Solution

Use Variable when you want to vary (modify) the quantity you are declaring, Constant when you don't. Or Signal if you want to vary it AND it's shared between different processes, ports or components.

But remember that Signal has different update semantics, avoiding the hazards and errors that can occur if you shared variables between processes in any language.

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