multiplying two 32-bit operand in verilog

Question

I have written multiplier in verilog which get two 32 bit operands and return a 64 bit output. I tested this code for 5 bit it worked properly but when I run this code nothing will be happened and also I can not stop or end simulation ModelSim. Do you have any idea about this problem?

    module multiplier_always(operand1,operand2,product);
input [31:0] operand1 ,operand2;
output reg [63:0] product; 

reg [63:0] op1;
reg [31:0] op2,addres,subres;
reg [64:0] subres2,result,addres2,opp1;
reg [2:0] i=0;



always@(*)
begin
        op1 = {32'b0,operand1};
        opp1 = {op1,1'b0};

for(i=0;i<32;i=i+1)
begin
case(opp1[1:0])
2'b00:begin
            opp1 = {opp1[64],opp1[64:1]};
            end

2'b01:begin
                addres = opp1[64:6]+ operand2; 
                addres2 = {addres,opp1[32:0]}; 
                opp1 = {addres2[64],addres2[64:1]}; 
            end

2'b10:begin 
                subres = opp1[64:6]+ (~operand2+1);
                subres2 = {subres,opp1[32:0]}; 
                opp1 = {subres2[64],subres2[64:1]};
            end

2'b11:begin
            opp1 = {opp1[64],opp1[64:1]};//shift
            end

endcase
end
product = opp1[64:1];

end
endmodule

Answer 1

Infinite loop as reg [2:0] i will always be less less than 32; i+1 is 0 when i==7. Change to integer i or reg [5:0] i.