Port (
data_out : out integer range -128 to 127
type ramtype is array (0 downto 29) of integer range -128 to 127;
signal ram : ramtype;
signal sine_wave : ramtype :=(0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);
signal clk :STD_LOGIC;
variable count : integer := 0;
variable inc : integer := 0;
constant period :time := 10 ms; -- 100 hz clk frequency
begin
process(clk)
begin
if rising_edge (clk) then
LINE:53 inc <= inc + 1; -- error
for i in 0 to 29 loop
data_out <= sine_wave(count);
end loop;
end if;
end process;
LINE 61: process(inc)
begin
clk <= not clk after period/2;
end process;
Line 53: Use := to assign to variable inc Line 61: Sensitivity list can have only static signal name
I need a concurrent statament for line 53 bu the compiler is suggesting an other thing, and also the sensitivity list is not being accepted Line 61: Sensitivity list can have only static signal name
i want to generate a sine wave where my clk frequency is 100 hz, and i want to sample it accordingly on every posedge of the clock
I did this earlier to find all problems with the portion of your code you did share. It's still not clear what inc was doing in the clock process sensitivity list.
The clock process has been modified to output one complete waveform only. Note both inc and count are declared as signals.
The range direction for ramtype has been changed from 0 downto 29 to 0 to 29.
I set the default value for clk to '0' which allows not clock to not provide an 'U' (see the not truth table from package std_logic_1164:
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
clk has to have an initial value of '0' (or 'L') or '1' ( or 'H') to make the clock process work in simulation.
Your code fragment modified to analyze, elaborate, and simulate:
library ieee;
use ieee.std_logic_1164.all;
entity sinewave is
end entity;
architecture foo of sinewave is
-- Port (
-- data_out : out integer range -128 to 127
signal data_out: integer range -128 to 127;
type ramtype is array ( integer range 0 to 29) of -- was downto
integer range -128 to 127;
-- signal ram : ramtype;
constant sine_wave: ramtype := (
0, 16, 31, 45, 58, 67, 74, 77, 77, 74, 67, 58, 45, 31, 16,
0,-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16
);
signal clk :STD_LOGIC := '0'; -- so not clk gives '1' or '0'
signal count : integer range 0 to 29 := 0;
signal inc : integer := 0;
constant period :time := 10 ms; -- 100 hz clk frequency
begin
process(clk)
begin
if rising_edge (clk) then
LINE_53: inc <= inc + 1; -- error
if count = 29 then -- count is index pointer to sine_wave
count <= 0;
else
count <= count + 1;
end if ;
-- for i in 0 to 29 loop
data_out <= sine_wave(count);
report "data_out <= " & integer'IMAGE(sine_wave(count));
--end loop;
end if;
end process;
LINE_61: process -- modified to show every element of sine_wave once
begin
wait for period/2;
clk <= not clk; -- after period/2;
if Now > 29.5 * period then
wait;
end if;
end process;
end architecture;
Note how count is used as the index to sine_wave, so I added an increment to it. It would seem redundant to have both inc and count.
The for loop got dropped as I explained in the comment because it doesn't do anything, simply repeating the same sine_wave assignment 30 times. It doesn't affect simulation.
I made his into a test bench because you provided a clock process.
When run the report statements output the count indexed sine_wave value as a display for purposes of demonstration yielding:
ghdl -r sinewave
sine.vhdl:37:13:@5ms:(report note): data_out <= 0
sine.vhdl:37:13:@15ms:(report note): data_out <= 16
sine.vhdl:37:13:@25ms:(report note): data_out <= 31
sine.vhdl:37:13:@35ms:(report note): data_out <= 45
sine.vhdl:37:13:@45ms:(report note): data_out <= 58
sine.vhdl:37:13:@55ms:(report note): data_out <= 67
sine.vhdl:37:13:@65ms:(report note): data_out <= 74
sine.vhdl:37:13:@75ms:(report note): data_out <= 77
sine.vhdl:37:13:@85ms:(report note): data_out <= 77
sine.vhdl:37:13:@95ms:(report note): data_out <= 74
sine.vhdl:37:13:@105ms:(report note): data_out <= 67
sine.vhdl:37:13:@115ms:(report note): data_out <= 58
sine.vhdl:37:13:@125ms:(report note): data_out <= 45
sine.vhdl:37:13:@135ms:(report note): data_out <= 31
sine.vhdl:37:13:@145ms:(report note): data_out <= 16
sine.vhdl:37:13:@155ms:(report note): data_out <= 0
sine.vhdl:37:13:@165ms:(report note): data_out <= -16
sine.vhdl:37:13:@175ms:(report note): data_out <= -31
sine.vhdl:37:13:@185ms:(report note): data_out <= -45
sine.vhdl:37:13:@195ms:(report note): data_out <= -58
sine.vhdl:37:13:@205ms:(report note): data_out <= -67
sine.vhdl:37:13:@215ms:(report note): data_out <= -74
sine.vhdl:37:13:@225ms:(report note): data_out <= -77
sine.vhdl:37:13:@235ms:(report note): data_out <= -77
sine.vhdl:37:13:@245ms:(report note): data_out <= -74
sine.vhdl:37:13:@255ms:(report note): data_out <= -67
sine.vhdl:37:13:@265ms:(report note): data_out <= -58
sine.vhdl:37:13:@275ms:(report note): data_out <= -45
sine.vhdl:37:13:@285ms:(report note): data_out <= -31
sine.vhdl:37:13:@295ms:(report note): data_out <= -16
Your 10 msec clock period means the sine wave is 3.333.. Hz.