Entries for Subprograms in VHDL

Question

i have two functions in my code :

 function derivative(error, previous_error, dt :in std_logic_vector(7 downto 0)) return std_logic_vector is
  variable derivative_val: std_logic_vector(15 downto 0);
  begin
      derivative_val := div(sub(error,previous_error),dt);
      return derivative_val;
  end derivative;


function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is
    variable v_TEST_VARIABLE1 : integer;
    variable v_TEST_VARIABLE2 : integer;
    variable n_times: integer:=1;
    variable product: integer:=0;
    begin 
       v_TEST_VARIABLE1 := to_integer(unsigned(num1)) ; 
       v_TEST_VARIABLE2 := to_integer(unsigned(num2)) ;
      for n_times in 1 to v_TEST_VARIABLE2 loop
        product:=product + v_TEST_VARIABLE1;
      end loop;
    return std_logic_vector(to_unsigned(product,16));
  end mul;

In the later half I am trying to assign a variable.

 variable derivative_term: std_logic_vector(15 downto 0) := x"0000";
  derivative_term := mul(mul(Kp,Td), derivative(error, previous_error,dt));

On compilation, I am getting :

No feasible entries for subprogram "mul".

Is there any other way to use it? thanks in advance.

Answer 1

The mul function takes arguments num* with type std_logic_vector(7 downto 0) thus length 8, and returns result with type std_logic_vector of length 16.

So when calling mul(mul(...), ...) the outer mul gets first argument with length 16 of type std_logic_vector, which does not match the required argument length for the function.

Instead of writing you own multiplication function, you could use the "*" from ieee.numeric_std, which can be used as:

slv_16_0 <= std_logic_vector(unsigned(slv_8_0) * unsigned(slv_8_1));

It also handles unknown values, like 'X', and resulting length is sum of length for the two arguments.