Force VHDL to use generic over constant

Question

I have some VHDL where a generic is the same name as a constant in an imported package. NCSIM seems to use the value of the constant from the package over the generic.

Rather than rename the generic is there a way I can force the scope to pick up the generic.

Answer 1

The identifier can be qualified with package or entity name in order to specify which of the overlapping identifiers that should be used. For example with the code:

package pkg is
  constant CONST : integer := 17;
end package;

...

use work.pkg;
use work.pkg.all;

entity mdl is
  generic(
    CONST : integer := 42);
end entity;

architecture sim of mdl is
begin
  process is
  begin
    report "CONST = " & integer'image(CONST);
    report "pkg.CONST = " & integer'image(pkg.CONST);
    report "mdl.CONST = " & integer'image(mdl.CONST);
    wait;
  end process;
end architecture;

The result with ModelSim is:

# ** Note: CONST = 42
# ** Note: pkg.CONST = 17
# ** Note: mdl.CONST = 42

However, the problem origins from "pollution" of the name space with use work.pkg.all, so a cleaner solution is to avoid pollution in the first place with use work.pkg, and then force qualified names for references to identifiers in the package, except if that approach is unpractical.