Integer or not, in vhdl

Question

is there any way to make that correct:

Comp : in  STD_LOGIC_VECTOR (7 downto 0);
EP : in  STD_LOGIC_VECTOR (2 downto 0);

(...)

signal pos : STD_LOGIC_VECTOR (7 downto 0):=(OTHERS => '0');
--signal i : STD_LOGIC_VECTOR (2 downto 0):=(OTHERS => '0');

(...)

--i<=EP;

    IF(Comp(to_integer(unsigned(EP)))='1') then
    pos(to_integer(unsigned(EP)))<='1';
elsif(Comp(to_integer(unsigned(EP-"001")))='1') then
   pos(to_integer(unsigned(EP-"001")))<='1';
elsif(Comp(to_integer(unsigned(EP-"010")))='1') then
   pos(to_integer(unsigned(EP-"010")))<='1';
elsif(Comp(to_integer(unsigned(EP-"011")))='1') then
   pos(to_integer(unsigned(EP-"011")))<='1';
elsif(Comp(to_integer(unsigned(EP-"100")))='1') then
   pos(to_integer(unsigned(EP-"100")))<='1';
elsif(Comp(to_integer(unsigned(EP-"101")))='1') then
   pos(to_integer(unsigned(EP-"101")))<='1';
elsif(Comp(to_integer(unsigned(EP-"110")))='1') then
   pos(to_integer(unsigned(EP-"110")))<='1';
else
   pos(to_integer(unsigned(EP-"111")))<='1';
end if;

I am getting the error: to_integer can not have such operands in this context. How can i fix it?

Answer 1

You simply have closing parenthesis in the wrong place converting ep to unsigned:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is  -- imaginary entity
    port (
        comp:   in  std_logic_vector (7 downto 0);
        ep:     in  std_logic_vector (2 downto 0)
    );
end entity;

architecture imaginary of foo is

    signal pos : std_logic_vector (7 downto 0):=(others => '0');
    --signal i : std_logic_vector (2 downto 0):=(others => '0');

begin

IMAGINARY_PROCESS:
    process
    begin
        if comp ( to_integer(unsigned(ep)) ) = '1' then
            pos( to_integer(unsigned(ep)) ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "001") )='1' then
            pos( to_integer(unsigned(ep) - "001") ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "010") ) = '1' then
            pos( to_integer(unsigned(ep) - "010") ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "011") ) = '1'  then
            pos( to_integer(unsigned(ep) - "011") ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "100") ) = '1' then
            pos( to_integer(unsigned(ep) - "100") ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "101") ) = '1' then
            pos( to_integer(unsigned(ep) - "101") ) <= '1';

        elsif comp( to_integer(unsigned(ep) - "110") ) = '1' then
            pos( to_integer(unsigned(ep) - "110") ) <= '1';

        else
            pos( to_integer(unsigned(ep) - "111") ) <= '1';
        end if;
    end process;
end architecture;

When you follow consistent formatting and indentation it's easier to detect.

It's not much harder to supply a test case that should analyze.

For your comment "All of them: to_integer can not have ..." to Shekar's answer that should have been all of them except the first one, which also demonstrates the value of example code that is complete enough to analyze (even if incorrect).