Can I use port mapping in behavioral method and is using process comppulsory in behavioral modelling VHDL

I have few doubt guys. Can I write a VHDL structural program with process? Can I write behavioral modeling without process? can i use port mapping in both behavioral and structural modeling? Is there any certain syntax rules for writing structural and behavioral in VHDL?

Solution

It's legal to mix any of those constructs (what's recommended is a different matter, and is somewhat subjective, so is probably off-topic here).

Behavioral modeling usually implies a process, and some (many?) designers avoid mixing processes with structural code (not me, in general), but there's nothing illegal about mixing them, and there's nothing "magical" about labeling an architecture with one or the other term.

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