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arraysverilog

Syntax for using an array of wires as input


I have the following module:

module add_8bit ( output wire co,
              output wire [7:0] r,

              input wire ci,
              input wire [7:0] x,
              input wire [7:0] y );

I am trying to use it via the following code:

 wire rbit [7:0];
 wire onebit [7:0];
 wire twocomp [7:0];

 wire tco, tci;

 add_8bit t9 ( tco, twocomp, tci, rbit, onebit );

It will not compile because of the last line. Why?


Solution

  • You've the wire declarations back to front in the second code snippet. Should be:

    wire [7:0] rbit;
    wire [7:0] onebit;
    wire [7:0] twocomp;