Verilog DFF Simulation Producing x for Output

Question

This should be the simplest issue to sort out but for some reason I just can't figure it out. I'm currently teaching myself Verilog and as an exercise have been developing very basic modules and test benches for these modules. One of these modules is the D Flip Flop (DFF). Here is the DFF module (no reset):

module DFF( clk, D, Q );
    parameter n = 1;    // DFF width
    input clk;
    input [n-1:0]  D;
    output [n-1:0] Q;
    reg [n-1:0] Q;

    always @( posedge clk ) begin
        Q <= D;
    end
endmodule

And here is the test bench:

module DFF_tb;
    reg clk, D;
    reg Q;

    DFF #(1) DUT ( clk, D, Q );

    initial begin
        clk = 1'b0;
        forever #10 clk = ~clk;     // Generate clock
    end

    initial begin   
        D = 0;                          // Check D = 0
        if ( Q !== 0 ) $display( "[FAIL] Q = 0" );

        #40 D = 1;                      // Check D = 1
        #40
        if ( Q !== 1 ) $display( "[FAIL] Q = 1" );

        $finish;                            // Complete test
    end
endmodule

And here is the simulation:

The test bench reg Q stays x for the duration of the simulation (thought Q[0] doesn't...).

Any idea why? Thanks!

Answer 1

You don't reset your flop, therefore before the first clock edge, Q does not have any known value.

Usually a flop has an async reset, which should be asserted at the beginning of the simulation in your test bench. The always block in your FF should be:

always @( posedge clk or posedge reset ) begin
  if (reset)
     Q <= '0;
  else
     Q <= D;
end

Also, you don't need to define Q as a reg. It can be a wire. Working code on edaplayground.com