VHDL clock divider works on board but fails in simulation

Question

I'm presently trying to use VHDL to design a traffic light controller, which I'm programming on an Altera EPM240T100C5 with a custom expansion board for displaying the traffic lights. As the slowest clock setting on the board is still faster than I would like, I've needed to write a clock divider which I did as so:

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

entity clockdivider is 
    port
    (
        clkin :  in  std_logic;
        dividedclk :  out  std_logic
    );
end clockdivider;

architecture divider of clockdivider is 

signal  J :  std_logic;
signal  K :  std_logic;


begin
J <= '1';
K <= '1';


process(clkin)
variable tempdividedclk : std_logic;
begin
if (rising_edge(clkin)) then
    tempdividedclk := (NOT(tempdividedclk) AND J) OR (tempdividedclk AND (NOT(K)));
end if;
    dividedclk <= '0';
    dividedclk <= tempdividedclk;
end process;

END divider;

This runs fine on the board but in the simulator (ModelSim) the "dividedclk" output fails to ever initialise to anything. I was wondering if anyone had any idea why?

Answer 1

At the beginning of the simulation, "tempdividedclk" is initialized to "unitialized". When a clock edge occurs, tempdividedclk will be assigned to (not(U) and 1) or (U and 0), which is "undefined". To simulate correctly, tempdividedclk must be initialized either by a reset or just at simulation level. It works find on silicon because the "U" state will be either a 1 or a 0.