VHDL invert if to reduce nesting

For C#, JetBrains ReSharper often suggests that you invert your if statements to reduce the number of nested if-statements.

For example, it suggests that the code below:

private void Foo()
{
    if (someCondition)
    {
        // Some action
    }
}

could be converted to:

private void Foo()
{
    if (!someCondition) return;
    // Some action
}

Is there a similar way to do this with VHDL code? Even if it is possible, is there a good reason to avoid this coding style in VHDL?

I am wondering if it possible to achieve something like this in VHDL

process(clock)
begin
    if (rising_edge(clock)) then
        -- Some action
    end if;
end process;

becomes

process(clock)
begin
    if (not rising_edge(clock)) then
        return;
    end if;

    -- Some action
end process;

Solution

The strategy you suggest is called early return because you are returning from a function early, before reaching its end. It can be done in VHDL and it is as useful as in other languages, but the downside is that it can only be used in subprograms. You cannot "return" from a process.

In theory, you could move the code from inside your process to a procedure, but it would not help achieve what you want. I suggest that you read section 6.3 - Concurrent Procedure Call Statements from Ashenden's Designer's Guide to VHDL to understand the details. In short, there are many restrictions to how the wait statement can be used in a procedure.