Implementing the PMod-ALS on the Basys2 Board in VHDL

I'm attempting to use the ALS Pmod with the Basys2 board in VHDL. How would I go about doing so?

Solution

With a 3-wire SPI™ communication interface. The Texas Instruments ADC081S021 Single Channel, 50 to 200 ksps, 8-Bit A/D Converter (PDF data sheet) is intended to be polled. Note from the TI datasheet you don't need a full SPI slave interface, it's read only, a simple port. From the schematic for the PMOD-ALS it appears it operates in continuous tracking mode.

Procedure call through different packages in VHDL
How to form a Qualified Expression of an Array Type with a Single Element?
VHDL error, unsigned on the LHS and RHS of assignment
Converting 8 bit binary to BCD value
Generate random values in VHDL function
VHDL Type Conversion Error: cannot convert type "universal_integer" to type "MemoryArray"
Port mapping only working in some entities
VHDL compiler exiting error
Vivado VHDL: attribute 'stable not implemented
VHDL signal not assigned in every case statement
Error when trying to read binary file in VHDL
Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
What is the utility of a "clock'event" if the sensitivity list has a single signal and is tested at 1?
Why am I not able to write to/read from custom AXI lite peripheral's registers
Verilog slice direction differs from VHDL
My counter "4-digit BCD Counter" does not work well!
With the MESI protocol, a write hit also stalls the processor, right?
Compiling VHDL file with ```ghdl -a``` encountered error ```ghdl:error: installation problem: ghdl1-llvm not found```
VHDL if statement precedence
Generate read-address and write address for zig-zag scan of NxN matrix
Where to force xilinx ISE to use block-rams?
FPGA efficient (a)synchronous resets
Can an embedded configuration be used for an instance inside a generate?
Weak 'H', Pullup on inout bidirectional signal in simulation
VHDL Coding .. conversion from integer to bit_vector
Viterbi Decoder VHDL project
Timing simulation in Vivado giving an error
When should I use a function over a procedure?
VHDL-2008 to_01 conversion
Uninitialized signal value for unknown reason