When running the following trivial code with ModelSim 10.1d
program test;
initial begin
$display("hello world");
end
endprogram
I'm seeing Error loading design
. The issue can be reproduced here: http://www.edaplayground.com/s/4/807
I know that ModelSim does not support SV assertions/coverage, but what about program
blocks?
ModelSim does not support the following SystemVerilog constructs that are supported in Questa:
In any case, I do not recommend the use of program
blocks for any user. See http://go.mentor.com/programblocks