How to handle a BUS in Verilog with multiple drivers

Question

I'm trying to connect multiple modules in verilog sharing a common "BUS" of size 16bits. I'm having trouble connecting multiple inputs(drivers) to the BUS. When I attach more then one driver, I get an error within Xilinx.

Signal BUS in unit {Top_Module_Name} is connected to following multiple drivers:

The code I have for the modules are

input         en;
output [15:0] BUS;
reg    [15:0] data;

if (en) begin BUS = data;
else BUS = 16'dZ;

In the top module I have something similar to

module1(en1,wBUS);
module2(en2,wBUS);
module3(en3,wBUS);

I have a controller controlling enables with 1 hot encoding.

Answer 1

Your BUS output is not a reg, but a wire. To use BUS in a IF statement (inside a combinational always of course) BUS has to be defined as reg.

Something like this:

module something (input en, 
                  output reg [15:0] bus
                 ); 
  reg [15:0] data = 16'hABCD;  // some value;

  always @* begin
    if (en)
      bus = data;
    else
      bus = 16'hZZZZ;
  end
endmodule

If bus is going to be a wire...

module something (input en, 
                  output [15:0] bus
                 ); 
  reg [15:0] data = 16'hABCD;  // some value;
  assign bus = (en)? data : 16'hZZZZ;
endmodule