The question is: for foo.c
, a .c
file used elsewhere in a larger project, should the foo.o
object file compilation target in the Makefile list foo.h
as a dependency?
foo.o: foo.c foo.h
$(CC) $(CFLAGS) -c -o foo.o foo.c
Is this simply a matter of convention?
This is my thinking up until now, and a stab at an answer:
It seems like any legitimate change to foo.h
would require a corresponding change to foo.c
. So, it's not necessary to list foo.h
as a dependency. However, it's probably a good idea, since we'd want to be notified immediately (via re-compilation) if changing foo.h
broke anything in foo.c
.
It's quite possible to have changes to header files that don't require changes to the .c files. For example, changing the values of constants, etc.
You always want to put all header files used by the source file as a prerequisite of the object file.