I have a TI DSP (TMS320F28235 if anyone cares) that I need to implement a FIFO for queueing information between main-loop code and an interrupt. High-speed execution for this queue is very critical but so is proper operation, and I'm not sure whether I can get away with implementing a FIFO without any explicit synchronization, or if not, where I have to disable interrupts.
I found this page and was wondering if anyone here could comment on its applicability.
The page you found is precisely applicable to your situation. It relies only on word reads and writes being atomic. It is vulnerable to hardware that silently reorders loads and stores. On the other hand, just about every other synchronization algorithm known to Man is also vulnerable to that particular crock.
If you feel like doing some serious computer archaeology, dig up the circular buffer descriptions for the CDC 6600 operating systems. CDC originally developed the technique for communicating between multiple physical processors in the 6600.