Comparing a long std_logic_vector to zeros

In simulation this works perfect. Is this is the best way of checking for zeros for a synthesisable code. What would be the resources generated?

signal vector_slv : std_logic_vector(2048 downto 0);
...
if (vector_slv = (vector_slv'range => '0')) then
  -- do something...

Is there any other optimal way to implement this solution considering h/w mapping (with optimal resource utilization).

I would be more interested in understanding the resources used.

Solution

There's no way that makes more or less sense for synthesis. Write the code that best expresses your intention.

If you are comparing a vector for all zeros, the following should all produce the same results, or you should file a serious bug against the tool!

signal vector_slv : std_logic_vector(2048 downto 0);
constant zeros : std_logic_vector(vector_slv'range) := (others => '0');
...
if vector_slv = (vector_slv'range => '0') then
  -- do something...
if vector_slv = zeros then
  -- do something...
if unsigned(vector_slv) = to_unsigned(0, vector_slv'length) then
  -- do something...

and indeed for shorter vectors which fit in an integer:

if intvar = 0 then

will be exactly the same as any 32-bit vector comparison.

_{(BTW, note there is no need for parentheses around the if condition - VHDL is not C :)}