Cases throwing unexpected when

Question

I'm making a statemachine in VHDL. My case is throwing an unexpected when error

case state IS
            --state 1 A
            WHEN s0=>
                --Half step
                if(FULL = '0' AND RIGHT = '1') then
                    state <= s1;
                else if (RIGHT = '0') then
                    state <= s7;
                end if;

                --Full step
                if (FULL = '1' AND RIGHT = '1') then
                    state <= s2;
                else if (RIGHT = '0') then
                    state <= s6;    
                end if;

            --State 2 A&B
            WHEN s1=>
                if(RIGHT = '0') then
                    state <= s0;
                else if (RIGHT = '1') then
                    state <= s2;
                end if;

However, when running a syntax check with xilinx ISE I'm greeted with a

ERROR:HDLParsers:164 Line 72. parse error, unexpected WHEN, expecting END

This happens 8 times in total. What am I doing wrong?

Answer 1

The if and end if are not balanced, so you will have to close the if with some more end if, or use elsif instead of else if.

You write:

if ... then
  ...
else if ... then
  ...
end if;

Even through your indentation shows this like balanced, it is not, since the right indentation would be:

if ... then
  ...
else 
  if ... then
    ...
  end if;

Then it is clear that the if and end if are not balance.

If you use elsif you can write it as:

if ... then
  ...
elsif ... then
  ...
end if;