OK, hello all.
My problem is as following: I have a very long array of 0's and 1's which I receive as an input on the FPGA. I will need to memorize that array somewhere but the problem is that I don't know the size of the array till the very last moment when the user precise it on the PC, or PLC (not sure yet) from where I get the array of 0's and 1's.
When the user decides, he will send the data. The first three numbers of the array, multiplied by 32 will give me the size of the std_logic_vector I need so I can save the incoming impulses.
The problem arising from here is that I cannot define the signal whenever I want, but I must do it in the beginning (when I still don't know the exact length).
Can someone help me out?
Thanks in advance, Rastapunk
Unfortunately on FPGA there is no way to define a variable-length signal/buffer. So in your case, you need to maintain a fixed-length buffer that can hold the maximum possible size of external data. If the size of such user data may exceed your FPGA memory size, you probably need an external RAM.
You need to define the data structure according to the format of your "data impulse". If your "data impulse" is parallel which means every bit comes at the same time, there must be a data bus that connects your FPGA with the data interface. You need to define a std_logic_vector with the same width of your data bus. The length of actual data cannot physically exceed the length of data bus, and you just ignore extra bits. (I guess this is not your case).
I assume that your data comes in multiple clock cycles. Then your data input must be driven by a clock, and there is also a fixed-lengh data bus (say the width is N). Your data type should not be std_logic_vector, but an array, whose element is a length-N std_logic_vector, with the grammar like this:
type input_type is array (max_len downto 0) of std_logic_vector (N-1 downto 0);
signal input_data: input_type;
where max_len is the maximum possible samples/words of your serial data. You also need another variable data_len to record the actual length of user input.
When you load the data, read one sample/word in each clock cycle. Load data_len in the first three cycles, and then fill input_data once an element in the rest cycles with increasing address, until your address equals to data_len-1.