Flip flop implementation with process. [VHDL]

Question

My question is in regards to the following code:

library ieee;
use ieee.std_logic_1164.all;

entity exam is port (
    I,CLK,RESET : in std_logic;
    Q : out std_logic
);
end entity;

architecture exam_arc of exam is
    signal temp_sig : std_logic;
begin
    process (CLK,RESET)
    begin
        if RESET = '1' then
            temp_sig <='0';
        elsif CLK'event and CLK='1' then
            temp_sig <= I;
        end if;
        Q <= temp_sig;
    end process;
end exam_arc;

It seems that this piece of code simulates a D flip flop that operates on rising edge of the clock, however the answer [this question is taken from an exam] to this question claims that this D flip flop operates on falling edge of the clock.

What kind of flip flop this VHDL code simulates?

Answer 1

It's a trick question. Note that the process wakes up on both rising and falling clock edges, and that the intermediate signal temp_sig is assigned on the rising_edge.

Put that together with the semantics of signal assignment (postponed assignment) and see what you get.

Cross check via simulation as Jim suggests...