vhdlxilinx
VHDL: Traffic Light State Machine not Synthesizing
So I'm creating a Traffic Light State Machine and I'm having a couple of issues with my code synthesizing. I've been trying to work it out for ages.
Issues:
- Counter Module not being connected with other modules
TopLevel Schematic: Viewable at https://i.sstatic.net/T8dRk.png
TopLevel.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel is Port ( MasterReset : in STD_LOGIC;
Clock : in STD_LOGIC;
CarEW : in STD_LOGIC;
CarNS : in STD_LOGIC;
PedEW : in STD_LOGIC;
PedNS : in STD_LOGIC;
debugLED : out STD_LOGIC;
Lights : out STD_LOGIC_VECTOR (3 downto 0));
end TopLevel;
architecture Behavioral of TopLevel is
-- Synchronized Button inputs --
signal PedEWButton : STD_LOGIC;
signal PedNSButton : STD_LOGIC;
signal CarEWButton : STD_LOGIC;
signal CarNSButton : STD_LOGIC;
--Reset, Clear and Count Signals --
signal ClearRegister : STD_LOGIC;
signal ResetCounter : STD_LOGIC;
signal Count: STD_LOGIC_VECTOR (8 downto 0);
-- Registered Ped Signals --
signal PedEWReg : STD_LOGIC;
signal PedNSReg : STD_LOGIC;
begin
-- Check For MasterReset and Sync Inputs
process (MasterReset, clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton)
begin
if (MasterReset = '1') then
debugLED <= '1';
CarNSButton <= '1';
CarEWButton <= '1';
PedEWButton <= '1';
PedNSButton <= '1';
elsif rising_edge(clock) then
CarEWButton <= CarEW;
CarNSButton <= CarNS;
PedEWButton <= PedEW;
PedNSButton <= PedNS;
end if;
end process;
-- Instantiate State Machine --
StateMachine:
entity work.TrafficStatesMachine
Port Map (
MasterReset => MasterReset,
Clock => Clock,
CarEWButton => CarEWButton,
CarNSButton => CarNSButton,
PedEWButton => PedEWReg,
PedNSButton => PedNSReg,
Counter => Count,
Lights => Lights,
ResetCounter => ResetCounter,
ClearRegister => ClearRegister
);
-- Instantiate Counter --
Counter:
entity work.Counter
Port Map (
MasterReset => MasterReset,
ResetCounter => ResetCounter,
Clock => Clock,
Counter => Count
);
-- Instantiate PedRegister --
PedRegister:
entity work.PedRegister
Port Map (
PedNSButton => PedNSButton,
PedEWButton => PedEWButton,
PedNSRegOut => PedNSReg,
PedEWRegOut => PedEWReg,
ClearRegister => ClearRegister
);
end architecture Behavioral;
TrafficStatesMachine.vhdl
--===================================================================
-- Traffic states Machine
--
-- A states Machine to interpret and manage traffic
--
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TrafficStatesMachine is
Port (
MasterReset : IN std_logic;
Clock : IN std_logic;
CarEWButton : IN std_logic;
CarNSButton : IN std_logic;
PedEWButton : IN std_logic;
PedNSButton : IN std_logic;
Counter : IN std_logic_vector(8 downto 0);
ResetCounter : OUT std_logic;
ClearRegister : OUT std_logic;
Lights : OUT std_logic_vector(3 downto 0)
);
end TrafficStatesMachine;
architecture Behavioural of TrafficStatesMachine is
type states_type is (EWCarGreen, EWPedGreen, EWAmber, NSCarGreen, NSPedGreen, NSAmber );
signal states: states_type;
begin
process( MasterReset, Clock, CarEWButton, CarNSButton, PedEWButton, PedNSButton, Counter )
begin
if (MasterReset = '1') then
states <= EWCarGreen;
elsif rising_edge(clock) then
case states is
when EWCarGreen =>
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedEWButton = '1') then
if (CarNSButton = '0') and (PedNSButton = '0') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
elsif (PedNSButton = '1') then
states <= EWAmber;
ResetCounter <= '1';
else
states <= EWCarGreen;
end if;
end if;
when EWPedGreen =>
ClearRegister <= '1';
ResetCounter <= '0';
if (Counter = "110010000") then
states <= EWCarGreen;
else
states <= EWPedGreen;
end if;
when EWAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedNSButton = '1') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
ResetCounter <= '1';
end if;
else
states <= EWAmber;
end if;
when NSCarGreen =>
ResetCounter <= '0';
ClearRegister <= '0';
if (Counter < "111111111") then
if (PedNSButton = '1') then
if (CarEWButton = '0') and (PedEWButton = '0') then
states <= NSPedGreen;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
elsif (Counter = "111111111") then
if (CarEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
elsif (PedEWButton = '1') then
states <= NSAmber;
ResetCounter <= '1';
else
states <= NSCarGreen;
end if;
end if;
when NSPedGreen =>
ResetCounter <= '0';
ClearRegister <= '1';
if (Counter = "110010000") then
states <= NSCarGreen;
else
states <= NSPedGreen;
end if;
when NSAmber =>
ResetCounter <= '0';
if (Counter = "011001000") then
if (PedEWButton = '1') then
states <= EWPedGreen;
ResetCounter <= '1';
else
states <= EWCarGreen;
ResetCounter <= '1';
end if;
else
states <= NSAmber;
end if;
end case;
end if;
end process;
process( states )
begin
case states is
when EWCarGreen => lights <= "0010";
when EWPedGreen => lights <= "0011";
when EWAmber => lights <= "0001";
when NSCarGreen => lights <= "1000";
when NSPedGreen => lights <= "1100";
when NSAmber => lights <= "0100";
when others => lights <= "0010";
end case;
end process;
end Behavioural;
Counter.vhdl
--===================================================================
-- Counter.vhdl
-- A counter to give time delays
--===================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( MasterReset : in std_logic;
Clock : in std_logic;
ResetCounter : in std_logic;
Counter : out std_logic_vector(8 downto 0));
end entity Counter;
architecture Behavioural of Counter is
signal Count : std_logic_vector(8 downto 0);
begin
Counter <= Count;
-- Produce Count sequence from 0 ... 512
process( MasterReset, Clock, ResetCounter)
begin
if (MasterReset = '1') then
Count <= "000000000"; -- start count from 0
elsif rising_edge(clock) then
if (ResetCounter = '1') then
Count <= "000000000";
elsif (Count < "111111111") then
Count <= Count + "000000001";
else
Count <= "111111111";
end if;
end if;
end process;
end architecture Behavioural;
PedRegister.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PedRegister is
Port ( ClearRegister : in STD_LOGIC;
PedNSButton: in STD_LOGIC;
PedEWButton : in STD_LOGIC;
PedNSRegOut : out STD_LOGIC;
PedEWRegOut : out STD_LOGIC);
end PedRegister;
architecture Behavioral of PedRegister is
signal PedNSReg : STD_LOGIC;
signal PedEWReg : STD_LOGIC;
begin
PedNSRegOut <= PedNSReg;
PedEWRegOut <= PedEWReg;
process (PedNSButton, PedEWButton, ClearRegister)
begin
if ClearRegister = '1' then
PedNSReg <='0';
elsif PedNSButton = '1' then
PedNSReg <='1';
else
PedNSReg <= '0';
end if;
if ClearRegister = '1' then
PedEWReg <= '0';
elsif PedEWButton = '1' then
PedEWReg <='1';
else
PedEWReg <= '0';
end if;
end process;
end Behavioral;
TopLevel.ucf
##################################################
# #
# Pin Assignments for Digilent C-Mod C2 Module #
# Traffic Light Hardware #
# #
##################################################
# The C-MOD Pin numbers are shown in the COMMENTS=20
# e.g. CMOD-P35 is pin 35 of the module and is (usualy) used for the = Clock input
# The following 3 CPLD pins have special on-chip Clock buffers
# Usually uncomment one Clock line as required
NET "Clock" LOC =3D "p1"|IOSTANDARD=3DLVCMOS33; # CMOD-P35 - GCK2, = Global Clock input
#NET "Clock" LOC =3D "p43"|IOSTANDARD=3DLVCMOS33; # CMOD-P33 - GCK0, = Global Clock input, May be used for I/O
#NET "Clock" LOC =3D "p44"|IOSTANDARD=3DLVCMOS33; # CMOD-P34 - GCK1, = Global Clock input, May be used for I/O
# System level constraints
Net Clock TNM_NET =3D Clock;
Timespec TS_Clock =3D PERIOD Clock 1 us; # adjust to suit Clock
# Convenient to allocate a Reset pin
NET "MasterReset" LOC =3D "p30"|IOSTANDARD=3DLVCMOS33; # CMOD-P18 - = GSR, Global Set/Reset
Net "Reset" TIG; # No timing constraint on system reset
#NET "" LOC =3D "p12"|IOSTANDARD=3DLVCMOS33; # CMOD-P1
#NET "" LOC =3D "p13"|IOSTANDARD=3DLVCMOS33; # CMOD-P2
#NET "" LOC =3D "p14"|IOSTANDARD=3DLVCMOS33; # CMOD-P3
#NET "" LOC =3D "p16"|IOSTANDARD=3DLVCMOS33; # CMOD-P4
# CMOD-P5-8 - N/C
#NET "" LOC =3D "p18"|IOSTANDARD=3DLVCMOS33; # CMOD-P9
NET "debugLED" LOC =3D "p19"|IOSTANDARD=3DLVCMOS33; # CMOD-P10
#NET "clockLED" LOC =3D "p20"|IOSTANDARD=3DLVCMOS33; # CMOD-P11
#NET "" LOC =3D "p21"|IOSTANDARD=3DLVCMOS33; # CMOD-P12
#NET "" LOC =3D "p22"|IOSTANDARD=3DLVCMOS33; # CMOD-P13
#NET "" LOC =3D "p23"|IOSTANDARD=3DLVCMOS33; # CMOD-P14
#NET "LEDs<0>" LOC =3D "p27"|IOSTANDARD=3DLVCMOS33; # CMOD-P15
#NET "LEDs<1>" LOC =3D "p28"|IOSTANDARD=3DLVCMOS33; # CMOD-P16
#NET "LEDs<2>" LOC =3D "p29"|IOSTANDARD=3DLVCMOS33; # CMOD-P17
# CMOD-P18 - GSR, Global Set/Reset - see above
# CMOD-P19 - N/C
# CMOD-P20 - Vcc
# CMOD-P21 - Gnd
#NET "" LOC =3D "p31"|IOSTANDARD=3DLVCMOS33; # CMOD-P22 - GTS2, Global = Tristate control
#NET "" LOC =3D "p32"|IOSTANDARD=3DLVCMOS33; # CMOD-P23 - GTS3, Global = Tristate control
#NET "" LOC =3D "p33"|IOSTANDARD=3DLVCMOS33; # CMOD-P24 - GTS0, Global = Tristate control
#NET "" LOC =3D "p34"|IOSTANDARD=3DLVCMOS33; # CMOD-P25 - GTS1, Global = Tristate control
NET "CarEW" LOC =3D "p36"|IOSTANDARD=3DLVCMOS33; # CMOD-P26
NET "CarNS" LOC =3D "p37"|IOSTANDARD=3DLVCMOS33; # CMOD-P27
NET "PedEW" LOC =3D "p38"|IOSTANDARD=3DLVCMOS33; # CMOD-P28
NET "PedNS" LOC =3D "p39"|IOSTANDARD=3DLVCMOS33; # CMOD-P29
NET "Lights<0>" LOC =3D "p40"|IOSTANDARD=3DLVCMOS33; # CMOD-P30
NET "Lights<1>" LOC =3D "p41"|IOSTANDARD=3DLVCMOS33; # CMOD-P31
NET "Lights<2>" LOC =3D "p42"|IOSTANDARD=3DLVCMOS33; # CMOD-P32
NET "Lights<3>" LOC =3D "p43"|IOSTANDARD=3DLVCMOS33; # CMOD-P33 - = GCK0, Global Clock input, May be used for I/O
#NET "Clock" LOC =3D "p44"|IOSTANDARD=3DLVCMOS33; # CMOD-P34 - GCK1, = Global Clock input, May be used for I/O
# CMOD-P35 - GCK1, Global Clock inputs, see above
#NET "" LOC =3D "p2"|IOSTANDARD=3DLVCMOS33; # CMOD-P35
#NET "" LOC =3D "p3"|IOSTANDARD=3DLVCMOS33; # CMOD-P36
#NET "" LOC =3D "p4"|IOSTANDARD=3DLVCMOS33; # CMOD-P37
#NET "" LOC =3D "p5"|IOSTANDARD=3DLVCMOS33; # CMOD-P38
#NET "" LOC =3D "p6"|IOSTANDARD=3DLVCMOS33; # CMOD-P39
#NET "" LOC =3D "p8"|IOSTANDARD=3DLVCMOS33; # CMOD-P40
Solution
a similar situation was described here
in this case it was an issue with Xilinx ISE version. I copied your code and checked it with ISE 13.4 and the counter is connected 
however, relevant for your function is the "real" synthesis (check synthesis report) and not the RTL schematic visualisatoin.
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