Verilog instantiation error

Question

I'm having an issue simply calling a module for a JK flip flop. Our project is to make a state machine, and My logic is correct, but i'm getting an error that says "VHDL module instantiation error: can not connect instance ports both by error and by name"

the error is on line 67, which is the first instantiation of a JK_FF

EDIT: I'm assuming the problem has something to do with the register, given by this http://quartushelp.altera.com/11.1/mergedProjects/msgs/msgs/evrfx_veri_not_a_structural_net_expression.htm

but i'm really not sure how to fix this error.

//Project 2 "main" 
module Project2(q3, q2, q1, q0, w, z0, z1, CLK, RST, enable);
//honestly not too sure if I need the Q or not
reg q0,q1,q2,q3;
input enable, w, CLK, RST;
output q0,q1,q2,q3,z0,z1;

initial begin
//k3 <= 1'b1; // essentially k3 = 1
end

and(newClock, CLK, enable); // this is the ned clock

//now i do my assignments i'm guessing
not(wnot, w);
not(q3not, q3);
not(q2not, q2);
not(q1not, q1);
not(q0not, q0);

// j0 assignment
and(j0temp,w,q3not,q2not,q1not); 
and(j0temp1,wnot,q2);
and(j0temp2,wnot,q1);
or(j0,j0temp, j0temp1, j0temp2);

// k0 assignment
and(k0temp,q3not,q2not);
or(k0,wnot,q1, k0temp);

//j1 assignment
and(j1temp, wnot,q3not,q2not,q1not,q0not);
and(j1temp1,w,q2);
and(j1temp2,w,q0);
or(j1,q3, j1temp, j1temp1, j1temp2);

//k1 assignments
and(k1temp,w,q1);
and(k1temp1,q2,q0);
and(k1temp2,q3not,q2not,q1,q0not);
or(k1,k1temp,k1temp1,k1temp2);

//j2 assignments
and(j2temp,wnot,q0);
and(j2temp1,w,q1);
and(j2temp2,wnot,q3);
or(j2, j2temp,j2temp1,j2temp2);

//k2 assignments
or(k2,wnot,q1);

//j3 assignments
and(j3,wnot,q2,q1,q0);

//z0 assignments
and(z0temp,wnot,q0not,q2);
and(z0temp1,wnot,q1,q2);
or(z0,z0temp,z0temp1);

//z1 assignments
and(z1temp, wnot,q2);
and(z1temp1,wnot,q1,q0not);
and(z1temp2,q2,q1);
or(z1, z1temp, z1temp1, z1temp2);

//instantiate the flip flops
JK_FF y0(.j(j0),.k(k0),.CLK(newClock), .RST(RST), .Q(q0), .Qnot(q0not));
JK_FF y1(.j(j1),.k(k1),.CLK(newClock), .RST(RST), .Q(q1), .Qnot(q1not));
JK_FF y2(j2,k2,newClock, RST, q2, q2not);
JK_FF y3(j3,k3,newClock, RST, q3, q3not);



endmodule

//asynchronous reset JK flip flop module
module JK_FF(j,k,CLK,RST,Q, Qnot);
input j,k,CLK,RST;
output Q; // not sure what this does or if used
output Qnot;
reg    Q;
reg    Qnot;

always @(negedge CLK or negedge RST)

        if(RST)begin
        Q <= 0;
        Qnot <= 1;
        end
        else if(~j && k) begin
        Q <= 0;
        Qnot <= 1;
        end
        else if(~j && ~k) begin
        Q <= Q;
        Qnot <= Qnot;
        end
        else if(j && ~k) begin
        Q <= 1;
        Qnot <= 0;
        end
        else if(j && k) begin
        Q <= Qnot;
        Qnot <= Q;
        end

endmodule

Answer 1

Somewhere in the IEEE Std 1364 it states net and variable declarations must appear after post declarations. Should be somewhere in the Data Type section. I'll update my answer if I find the reference.

Easy fix: move line 4 reg q0,q1,q2,q3; below output q0,q1,q2,q3,z0,z1;.

Personally I prefer using the port declaration style introduced in IEEE Std 1364-2001, less lines of code and more readable.

module Project2(
  output reg  q3, q2, q1, q0,
  input  wire w, 
  output wire z0, z1,
  input  wire CLK, RST, enable );

Also note that you are missing a driver on k3 and it will give you problems with JK_FF y3

---

Citation Update:

From IEEE Std 1364-2001 section 12.3.3, and repeated in IEEE Std 1364-2005 section 12.3.3 and IEEE Std 1800-2012 section 23.2.2.1:

"If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration."