Use of Set in a Flip Flop

Question

1)I understand that reset is used in ASIC to start from a known state. Like

always @ (posedge clk or negedge reset)
begin 
if (reset)
//Initialize the signals
else 
//do something
end

But if this is the case , why don't we use set signal and start from a different state and end up eventually what the circuit is suppose to do ?It seems silly but I curious, that s it.I have never seen someone code like this.

 always @ (posedge clk or negedge set)
    begin 
    if (set)
    //Initialize the signals
    else 
    //do something
    end

2)Also , I read that it is necessary that reset signal should be modeled using if/else statement with reset in if condition. Can anyone give me an example how to do it otherwise ?

Answer 1

There is a slight mistake in the example in your question it should be:

always @ (posedge clk or negedge reset) begin 
  if (~reset) begin //<-- Reset when rest low
    //Initialize the signals
  end
  else begin 
    //do something
  end
end

The negedge reset will trigger when the signal is going low, therefore you want the reset condition to match. This is an Active Low reset. For an active high reset (Reset when reset == 1) you want:

always @ (posedge clk or posedge reset) begin //<--Posedge trigger reset
  if (reset) begin //<-- Reset when rest high
    //Initialize the signals
  end
  else begin 
    //do something
  end
end

The reset condition does not have to be to 0. It can be anything but it must be a known static value. ie NOT next_state or a+b etc. It is connected the reset pin of teh flip-flop and that is why we keep the name reset.

Active low resets are preferred in ASIC as when there is no power it is in reset. when the chip starts you often synchronously release the reset on the posedge of the clock. often for a minimum of 2 posedges. This avoids the reset glitching for small amounts of time.

Because you want the Active Low reset to be applied as the chip powers up so when powered up everything is in a known state we use asynchronous resets. With synchronous resets you have no idea what the first state will be. Synchronous resets are often used by state machines and filters which need to clear data. Asynchronous resets are used for power on reset (POR) to set known values.

The if (reset) else structure is used so that synthesis tools can recgonise it as a flip-flop with async reset, trying another structure may simulate fine, may even synthesise (incorrectly), but you could easily end up with hardware bugs which do not show in simulation making debugging very difficult.

You may be interested to read up on set-reset flip-flops (SR Flip-Flop). Which just a JK with out the Toggle function.

It may be implied using the following :

always @ (posedge clk or negedge reset or posedge set) begin 
  if (~reset) begin 
    //reset the signals
  end
  else if (set) begin
    //set the signals
  end
  else begin 
    //do something
  end
end