How to connect top module's input port to a components output port?

Question

I'm using Xilinx ISE 13.2.

I'm very new to VHDL and I'm having troubles connecting components. I have a top module and a component (defined in another file) defined as below:

entity kcpsm3_int_test is
    Port (      number_in  : in std_logic_vector(3 downto 0);
                    number_out  : out std_logic_vector(3 downto 0);
                    button      : in std_logic;
           interrupt_event : in std_logic;
                       clk : in std_logic);
    end kcpsm3_int_test;

component debounce_logic
Port ( clk   : in  STD_LOGIC;
       btn_in  : in  STD_LOGIC;
       btn_out : out  STD_LOGIC);
end component;

--port
db: debounce_logic
 port map(
            clk     => clk,
        btn_in  => button,
        btn_out  => btn_out);

I also defined a signal btn_out to connect those two. I can see how two other components (a processor and a ROM) are connected, but I could not manage to connect these two. I think I need to port the top module somehow but I don't know how to and I'm pretty much stuck here, how can I proceed? How can I connect the btn_out, output of debounce logic, to the input of the top-module??

Answer 1

What you have done is: declared a entity called kcpsm3_int_test declared a component called debounce_logic , which has been defined somewhere else. What you need to do next is: instantiate the component debounce_logic , and port map. it would look something like this.

db_1 : debounce_logic
PORTMAP (clk => clk,
         ....
         );

here is a link for detailed explanation.