VHDL library for basic elements

I am starting at VHDL and while trying to implement a circuit I found that I need basic elements like leading one/zero detectors or leading one/zero counters. Since I consider these basic I would like to know if there is a library to include.

If I have to put together my own implementations is there a collection where one can copy from or do I need to reinvent the wheel?

(I can google them one by one and find implementations in forums, however some of them seem quite bad/implemented not general enough (i.e. this multiplexer)).

Solution

One reason why the approach you suggest (a library of simple re-usable elements) doesn't catch on : you are often better off without them.

The example multiplexer you linked to illustrates the point quite well:

ENTITY multiplexer IS
PORT (
   a, b, c, d, e, f, g, h : IN STD_LOGIC;
   sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
   y : OUT STD_LOGIC
);
END ENTITY multiplexer;

given slightly better design, using the type system you could write (perhaps in a re-usable package)

subtype sel_type is natural range 0 to 7;

and then in your design, given the signal declarations

signal sel_inputs : std_logic_vector(sel_type);
signal sel        : sel_type;
signal y          : std_logic;

you could simply write

sel_inputs <= a & b & c & d & e & f & g & h;
y          <= sel_inputs(sel);

with much less fuss than actually instantiating the multiplexer component.

Leading zero detectors look harder at first glance : they are generally implemented as clocked processes, or as part of a larger clocked process.

Recent trends in VHDL are moving towards a semi-behavioural style of synthesisable VHDL, where quite a lot is written in a sequential style within a single clocked process. This is best seen in the "single process state machine"; smaller, easier to understand and definitely more reliable * than the "two process" style still commonly taught.

(* unless your tools support the "process(all)" sensitivity list of VHDL-2008 for the combinational process.)

Within a clocked process (i.e. assume the following is inside if rising_edge(clk) then simple tasks like counting the leading zeroes in an array can be expressed using for loops; for example:

   for i in sel_type loop
      if sel_inputs(i) = '1' then
         zero_count <= sel_type'high - i;
      end if;
   end loop;

The last assignment will win; if h = '1' the count will be 0, otherwise if g = '1' the count will be 1, and so on.

Now it's not a one-liner unless you write a procedure for it (also synthesisable with most tools!) but compare it with the size of an entity instantiation (and interconnections).

Of course a library of procedures and functions can be useful; and (for less trivial tasks) the same is true for entities also, but in my opinion, making them general enough to be useful to all, without making them heavyweight, would be quite an achievement.