Verilog sequence of non blocking assignments

Question

Say the following code section (same block):

A <= 1
A <= 2

Will variable A always be assigned 2? or will there be a race condition and 1 or 2 will be assigned ?

My understanding of non blocking assignment is that it is up to the hardware to assign the variable A at a future time so it could be a random result. However, this is non intuitive. Simulations show that 2 always get assigned, but I would like to know if this is definitely the case for hardware synthesis.

Answer 1

A would be 2 in simulation, the last defined value takes effect. If they are not in the same block then there could be a race condition depending on the simulator scheduler as to which was defined last in simulation.

I have seen this technique used quite a lot and never seen any unexpected results after synthesis.

From Verilog IEEE 1364-2005 Section 11.4.1 Determinism

Statements within a begin-end block shall be executed in the order in which they appear in that begin-end block. Execution of statements in a particular begin-end block can be suspended in favor of other processes in the model; however, in no case shall the statements in a begin-end block be executed in any order other than that in which they appear in the source.

This is also in SystemVerilog-IEEE1800 2012 as section 4.6 Determinism

Usage of this might be a FSM which sparsely defines its outputs:

always @(posedge clk) begin
  out_one <= 1'b0;
  out_two <= 1'b0;
  out_thr <= 1'b0;
  case (state)
    2'd1 : out_one <= 1'b1;
    2'd2 : out_two <= 1'b1;
    2'd3 : out_thr <= 1'b1;
  endcase
end