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binaryverilog

Verilog : Use of assign and always

module circuit_1 (a, b, c);
input [1:0J a,b;
output [3:0J c;
assign c = a + b;

If input a = 2'b11 and input b = 2'b10,

what value would output c have ? Please give a descriptive answer.

Also kindly tell me functionality of assign and always. I am a bit confused.

Solution 
  • c = 4'b0101      // Output, implicitly a wire

    "assign" is used for net type declarations(Wire,Tri etc).Since wires change values according to the value driving them, whenever the operands on the RHS changes,the value is evaluated and assigned to LHS(simulating a wire)

    always - is used for registers + combinational logic. If it is always(@ posedge clk)- The event posedge clk triggers the always block and the logic inside the block is evaluated and assigned.

    always @ (*) - If something in the RHS of the always block changes,that particular expression is evaluated and assigned.

    Imagine assign as wires and always blocks as registers (For now) , as their behavior is same.