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hardwarevhdlxilinxhdlmodelsim

Is a <= a + 1 a good practice in VHDL?

If I write the statement to assign a to be a+1 in a VHDL process, is it a good practice?

I am confused about this because the simulator works fine, but when I try to implement it in FPGA the synthesis tool complains about creating latches.

What does this mean?

Solution

  • you should do such a statement only in a clocked process. if you want to have it synthesised, an additional initialisation (reset) is suggested. might look as follows:

    process(clk, reset)
begin
   if reset='1' then
      a <= 0;
   elsif rising_edge(clk) then
      a <= a + 1;
   end if;
end process;