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VHDL - Design Library Does Not Contain Unit

I have the following architecture:

architecture datapath of DE2_TOP is
begin
U1: entity work.lab1 port map (
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
);
end datapath;

I am getting the following error: Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work" does not contain primary unit "lab1" on the line: U1: entity work.lab1 port map (. Anyone know what is causing this?

Solution

  • You need to have compiled at least the entityfor lab1 before you compile DE2_TOP