Problems opening files from a VHDL process into an entity instantiated twice: name conflicts

Question

I have an entity in VHDL which has the following structure:

-- Imports...
entity myentity is
  port (..specifying in and out signals..);
end myentity;

architecture beh_myentity of myentity is
  begin
    process(..sensitivity list..)
      -- Some variables
      file myfile : text open write_mode 
                    is "myentlog.txt";  -- <== My problem is here!!!
        begin
          -- ..The process body..
    end process;
end beh_myentity;

No problems in opening the file, everything works! I have a problem. When I create a testbench and run it I usually create one single instance of my entity. But in my case I now need to put two instances. My problem is that I will have conflicts with file name and one process will inevitably fail opening and writing the (same) log file.

I would like to solve this, so here the questions:

1. In my port I have signals, is it ok to append a signal value to the name of the file? I am afraid this is not the best thing to do (not even know if such a thing would work).

2. Is there a way to get a variable representing the instance name of the entity in the testbench?

3. is there a way to pass a string to the entity so that I can attach it at the end of the file name?

Thankyou

Answer 1

Either a signal of type string, containing the filename; or a generic (again, of type string).

The signal allows you to assign different filenames to the same entity at different times in your testbench - using VHDL-1993 or later, the architecture can call file_open() with the new filename.

The generic gives a fixed filename to each different entity.

Use whichever is simplest for your application.

Your specific questions : 1) Yes , if the signal is a string, you can either pass in the whole filename as a string or pass in a suffix. Because you are generating the string at runtime you need VHDL-93 (or later) syntax

process (...) is
file my_file;
begin
   file_open(my_file, base_name & suffix & ".txt", read_mode);
   ...
   file_close(my_file);
end process;

2) Best way is to generate the filename in the testbench and pass it in. However an out port from the entity would work! Naturally you can't synthesise this entity...

3) Of course...

entity myentity is
  generic ( base_name : string := "testfile");
  port    (suffix : in string);
end myentity;

will pass in the strings you needed in (2).

If you must use VHDL-87 syntax, as in your example, pass the whole name in as a generic:

file myfile : text open write_mode is base_name;