What is "??" in Verilog casez?

Question

I have a module below:

module bai1c(a, b0, b1, b2, b3, c);
    input [2:0] a;
    input [3:0] b0, b1, b2, b3;
    output reg[3:0] c;

    always @(a or b0 or b1 or b2 or b3) begin
        casez(a)
            3'b000: c = b0;
            3'b001: c = b1;
            3'b010: c = b2;
            3'b011: c = b3;
            3'b1??: c = 4'b0000;
        endcase
    end
endmodule

What kind of circuit will be synthesized? When the condition 3'b1?? happen? (what ?? is?)

Answer 1

? is a don't care value - i.e. it will match either 0, 1 or z. So the 3'b1?? case will occur whenever the first bit is 1, no matter what the other two bits are.

The circuit is basically a 4:1 multiplexer, selecting one of b0,b1,b2,b3, with an added select bit on a that forces the output to 0, no matter what the other two select bits are.