How Can i eliminate inout signal for my vhdl Adder?

Question

I have written the following VHDL code which is the component of a Fast Adder. The fast adder consists of an 8by8 register hooked up to adder whose code is below. How can i eliminate the use of inout Read_Adress. I want Read_Adress to be out std_logic_vector not inout?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Entity Adder is
port(
        Clock_50_MHZ :in std_logic;
        En :in std_logic;
        Data_Registerfile : in std_logic_vector(7 downto 0);
        Read_Address: inout std_logic_vector(2 downto 0) := "000";
            Output : out std_logic_vector(11 downto 0)
 );
 end Adder;

 Architecture arch of Adder is
 Signal result : unsigned (11 downto 0):="000000000000";
 Signal regData: std_logic_vector(7 downto 0);

 Begin
 regData <= Data_Registerfile;
 Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ)  then
    if (En = '1') then
        if(Read_Address = "000") then
            result <= "000000000000" + unsigned(regData);
            Read_Address <= Read_Address + 1;
        elsif(Read_Address = "111") then
            Output <= std_logic_vector( result + unsigned(regData) );
            Read_Address <= "000";
        else
            result <= result + unsigned(regData);
            Read_Address <= Read_Address + 1;
        end if;
    end if;
end if;
 End Process;
end arch;

Answer 1

This is a classic inconvenience in VHDL: you can't use your out ports as signals (if you are used to Verilog, you often find yourself wanting to do that).

The best way that I know of is to create an extra dummy signal:

signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";

do the computation with that:

     Process(Clock_50_MHZ)
 Begin
 if rising_edge(Clock_50_MHZ)  then
     if (En = '1') then
         if(Read_Address_tmp = "000") then
             result <= "000000000000" + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         elsif(Read_Address_tmp = "111") then
             Output <= std_logic_vector( result + unsigned(regData) );
             Read_Address_tmp <= "000";
         else
             result <= result + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         end if;
     end if;
 end if;
  End Process;

and then link it to your output:

Read_Address <= Read_Address_tmp;