VHDL: unexpected END using functions

Question

I'm trying to synthesize some code I've found which essentially converts an 8-bit binary to BCD. The code uses functions and I'm having an error of the following;

Line #: parse error, unexpected END

The following is the behavior part of my code;

architecture Behavioral of bintobcd is


function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable bcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;

begin
for i in 0 to 7 loop  -- repeating 8 times.
    bcd(11 downto 1) := bcd(10 downto 0);  --shifting the bits.
    bcd(0) := bint(7);
    bint(7 downto 1) := bint(6 downto 0);
    bint(0) :='0';


    if (i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
        bcd(3 downto 0) := bcd(3 downto 0) + "0011";
    end if;

    if (i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
        bcd(7 downto 4) := bcd(7 downto 4) + "0011";
    end if;

    if (i < 7 and bcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.
        bcd(11 downto 8) := bcd(11 downto 8) + "0011";
    end if;


end loop;
return bcd;
end to_bcd;
end Behavioral;

The error points to my last line "end Behavioral". What am I doing wrong here?

Kind regards

Answer 1

The definition of an architecture is as follows:

architecture identifier of entity_name is
    architecture_declarative_part
begin
    architecture_statement_part
end optional(architecture) optional(architecture_simple_name) ;

Before you say end architecture, you need to say begin, and do the architecture statement part (which can be empty)