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optimizing VHDL code


I have made this VHDL code for writing to a USB-chip.

It all runs inside a case statement, where each operation (write, read, ect.) is implemented.

The two write register sections below are equal, only different by the address and data.

Can this be simplified using a procedure or something?

            -------- WRITE REGISTER ---------
            when s10 =>
                -- Txd Cmd
                txdata(7 downto 6) <=  "10";        -- CMD = register write
                txdata(5 downto 0) <=  "000100";    -- address
                state := s11;
            when s11 => 
                -- write reg
                if nxt = '1' then
                    txdata <= X"45";    -- output on clock rising edge when nxt is high
                    stp <= '1';                     
                    state := s12;
                end if;
            when s12 =>
                stp <= '0';                             
                txdata <= "00000000";       -- idle                 
                state := s20;

            -------- WRITE REGISTER ---------
            when s20 =>
                -- Txd Cmd
                txdata(7 downto 6) <=  "10";        -- CMD = register write
                txdata(5 downto 0) <=  "110101";    -- address
                state := s21;
            when s21 => 
                -- write reg
                if nxt = '1' then
                    txdata <= X"04";                                            
                    stp <= '1';                     
                    state := s22;
                end if;
            when s22 =>
                stp <= '0';                             
                txdata <= "00000000";       -- idle                 
                state := s30;

Solution

  • Yes, use a procedure. Is this not what you asked here already?

    Design VHDL state machine for initialization