Best VHDL design practice

Question

Question about best VHDL design practice.

When designing state machines, should I use a signal within the Architecture or use an variable. I have until now used variables, since they are "kinda" private to the process, and IMHO makes good sense because they should not be accesses outside the process. But is this good design practice?

type state_type is (s0,s1);  
signal state : state_type := s0;  

A : process(clk)
begin   
  if rising_edge(clk) then  
    case state is  
.....  
    end case;  
  end if;
end process;  

--This process uses a variable  
B : process(clk)  
  type state_type is (s0,s1);  
  variable state : state_type := s0;  
begin  
  if rising_edge(clk) then  
    case state is  
      .....  
    end case;  
  end if;
end process;  

Answer 1

I always use variables unless I need to communicate some value to another process. Because that's what signals are for.

Another potential benefit (or alternatively, something to watch as a violation of your coding standards!) of "localising the state variable" is that you can call the type and the variable state_type and state in two state machines in the same entity without them clashing...