I am trying to test a VHDL component, but I can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong?
For Inout port (for example in RAM):
....
port(
data :inout std_logic_vector (DATA_WIDTH-1 downto 0);
....
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
MEM_WRITE: process (address, cs, we, data, address_1, cs_1, we_1, data_1) begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;
-- Tri-State Buffer control
data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
-- Memory Read Block
MEM_READ: process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
else
data_out <= (others=>'0');
end if;
end process;
You assign data read and write for inout with a condition. When data is read, it is driven by another module. When it writes, it is driven by internal.