How to generate bitstream (.bin) file using Synplify

I am using Synplify version 9.6.2

I would like to generate a .bin file to load onto the FPGA. The output from Synplify is a .edn or.edf netlist.

Anyone know what is the process for doing this?

Solution

You have to take the EDIF netlist and feed it through Xilinx's tools (ISE) to get the EDF converted to a placed-and-routed design and then to a bitstream in .bin format.

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